CRC32 checksum validation for block transfer & I/O instructions
How it works: Each test patches a specific Z80 instruction to NOP, then runs a
comprehensive test sequence computing a CRC32 over the resulting CPU state (registers, flags, memory).
The checksum must match known-good values from real Z80 silicon.
LDIR is at prefix ED B0 â when replaced with NOP, the expected CRC is CC93B5EC
Running...
Click "Run All Tests" or "Test LDIR Only" to begin verification
đ Reference Checksums
Instruction
Opcode
Replacement
Expected CRC32
LDIR
ED B0
â NOP
CC93B5EC
LDDR
ED B8
â NOP
CD491C09
LDI
ED A0
â NOP
D1924DCA
LDD
ED A8
â NOP
3E5FD25A
CPI
ED A1
â NOP
B8B2A6A8
CPIR
ED B1
â NOP
A8D4B88F
CPD
ED A9
â NOP
C55E4666
CPDR
ED B9
â NOP
9ACA4FAB
No TAP loaded
P1
P1: â â â â = D-Pad | Z = Btn1 | X = Btn2 | Enter = Play/Pause
Type directly on keyboard | Shift = CAPS SHIFT | Ctrl/Alt = SYM SHIFT
Z80 CPU instruction verification via CRC32 checksums
đ§ Debug Panelâŧ
CPU Registers
Flags
VDP Registers
ULA State
Disassembly
Breakpoint
No breakpoint
Memory Viewer
No ROM Loaded0 FPSCycles: 0Mode: --ROM: 32KB | Cart RAM: 8KB | Sys RAM: 1KB